1. Field of the Invention
The invention relates to the architecture of memories in integrated circuit form. The invention can be applied more particularly in the field of EPROM or EEPROM type electrically programmable non-volatile memories.
The memories are organized in networks of cells forming a plurality of columns and a plurality of rows. The respective cells of each column are connected to a respective bit line and the respective cells of each row are connected to a word line. The bit line enables the transmission of an information element which provides the state of a memory cell located at the intersection of the bit line and a selected word line.
Read circuits are connected to the bit lines, possibly by means of a multiplexer if there are several bit lines for a single read circuit. Hereinafter, we shall consider a memory organized in eight-bit words, therefore comprising eight read circuits.
2. Discussion of the Related Art
A known memory architecture comprises a memory array comprising a network of memory cells associated with read circuits and reference memory cells. The reference cells are blank and may be placed outside the memory array or integrated into the memory array in the form of an additional row. Each reference cell is connected to a bit line called a reference line.
A schematic drawing of a memory of this kind is shown in FIG. 1. The memory has eight read circuits CL.sub.0, . . . , CL.sub.7, each read circuit CL.sub.k (k ranging from 0 to 7) being associated firstly with a plurality of reference lines LR.sub.0, LR.sub.i, LR.sub.i+7, LR.sub.i+15 . . . and secondly with a plurality of bit lines LB.sub.0, LB.sub.i, LB.sub.j+7, Lb.sub.i+15, etc. Transistors T.sub.i through T.sub.i+7 and T'.sub.i through T'.sub.i+7 enable the selection respectively of eight bit lines LB.sub.i through LB.sub.i+7 and eight corresponding reference lines LR.sub.i through LR.sub.i+7 during a memory word reading operation. During this reading operation, a control signal COL.sub.p coming from a column decoder is applied simultaneously to the control gate of transistors T.sub.i through T.sub.i+7 and T'.sub.i through T'.sub.i+7, turning these transistors on. Thus, for an eight-bit memory, the control signal COL.sub.p is applied simultaneously to the gate of eight transistors T.sub.i and eight transistors T'.sub.i (I=p*8) turning all these transistors on.
A memory cell C.sub.i is connected to bit line LB.sub.i. Memory cell C.sub.i consists of a selection transistor TS.sub.i and a floating-gate transistor TGF.sub.i that are series-connected. The drain of selection transistor TS.sub.i is connected to bit line LB.sub.i and its control gate is connected to a word line Lm.sub.j. The source of transistor TGF.sub.i is connected to the ground and its control gate receives a read voltage V.sub.L by means of two transistors TGC.sub.p and TC.sub.p that are series-connected. Transistor TGC.sub.p is a transistor providing access to the control gate of the transistor TGF.sub.i. Its source is connected to the control gate of transistor TGF.sub.i, its control gate is connected to word line LM.sub.j and its drain is connected to the source of control transistor TC.sub.p. Control transistor TC.sub.p receives read voltage V.sub.L at its source while signal COL.sub.p is applied to its control gate. Cell C.sub.i may have two states: an erase state in which a positive charge is trapped in the floating-gate of the floating-gate transistor and a programmed state in which a negative charge is trapped in the floating-gate of the floating-gate transistor. The conduction threshold is about -1V for the erased cell and 4V for the programmed cell.
Reference lines LR.sub.i comprise, in addition to transistor T'.sub.i, a floating-gate transistor called a reference transistor TR.sub.i that constitutes the reference cell. The reference cell is blank. This means that the floating-gate of transistor TR.sub.i is neither charged with electrical charges nor depleted of them. The source of transistor TR.sub.i is connected to a ground terminal and its drain is connected to the source of transistor T'.sub.i. Transistor TR.sub.i receives the read voltage V.sub.L at its control gate through a control transistor TC'.sub.p activated by signal COL.sub.p. The source of transistor TC'.sub.p is connected to the control gate of transistor TR.sub.i and its drain receives read voltage V.sub.L. The value of read voltage V.sub.L is usually equal to 1.5 volts in order to detect the programmed or erased state of a memory cell C.sub.i as well as the blank state of the reference cells.
FIG. 1 shows memory cells C.sub.0, C.sub.7, C.sub.i and C.sub.i+7 respectively located at the intersection of word line LM.sub.j and bit lines LB.sub.0, LB.sub.7, LB.sub.i and LB.sub.i+7. There is only one pair of transistors TGC.sub.p and TC.sub.p for eight adjacent memory cells, since eight of the memory cells are read simultaneously. FIG. 1 also shows corresponding reference lines LR.sub.0, LR.sub.7, LR.sub.i and LR.sub.i+7. Just as in the case of transistors TC.sub.p and TGC.sub.p, only one transistor TC'.sub.p is provided for eight reference cells. A particular word is read when (i) word line Lm.sub.j is active; (ii) signal COL.sub.p is applied to the eight control transistors TC.sub.p and TC'.sub.p respectively and eight transistors T.sub.i and T'.sub.i respectively and (iii) each read circuit receives a respective bit line and reference line of the word to be read.
During a memory read operation, the presence or absence of a current in the bit line connected to the selected cell is detected. A current of this kind exists if the cell is erased or blank, whereas a current does not exist if the cell is programmed. To detect the presence or absence of a current, the current flowing in the bit line is compared with the current flowing in the corresponding reference line.
An example of a known read circuit CL.sub.k is shown in FIG. 2.
The memory cell C.sub.i selected by word line LM.sub.j delivers an information element on the bit line LB.sub.i. The bit line LB.sub.i is precharged with voltage in a precharging stage by a precharging transistor TN1 whose function is to provide a precharging current to the bit line while limiting the precharging potential to a specified value, preferably in the region of one volt.
The corresponding reference line LR.sub.i is also precharged to an identical voltage value by a second precharging transistor TN2. During the reading stage, the reference line consumes current equivalent to that consumed by a blank memory cell.
Transistors TN1 and TN2 are preferably N channel transistors, their source being connected to bit line LB.sub.i and to reference line LR.sub.i respectively. To simplify the description, the gates of transistors TN1 and TN2 are shown as being connected to a biasing source Vpol. The value of voltage Vpol defines the upper limit of the precharging voltage of lines LB.sub.i and LR.sub.i.
To read the state of the cell C.sub.i, a comparison is made between the current consumed by the bit line LB.sub.i and reference line LR.sub.i. More specifically, the current consumed by the bit line is compared with a fraction of the current normally consumed by a blank cell.
To this end, the drains of transistors TN1 and TN2 are supplied by two arms of a current mirror with a copying ratio k that is smaller than 1. The first arm of the mirror has a copying transistor TP1 and the second arm has a reference transistor TP2. Transistor TP1 copies the current flowing in reference transistor TP2 with a ratio k. This ratio k is the ratio of the geometries of the transistors.
Copying transistor TP1 is a P channel transistor having its source connected to a supply terminal Vcc and its drain connected to the drain of transistor TN1.
In the same way, reference transistor TP2 is a P channel transistor having its source connected to supply terminal Vcc and its drain connected to the drain of transistor TN2.
The gates of transistors TP1 and TP2 are connected and the gate of reference transistor TP2 is connected to its drain. We thus have a standard current copying pattern.
A differential amplifier AD has its inputs connected to the drains of transistors TP1 and TP2 to measure the difference between the potentials at these two drains. This difference is zero if the currents in transistors TP1 and TP2 are in the ratio of geometries k. The output of amplifier AD gives a signal that provides an indication of whether the ratio of the currents is greater than k or smaller than k.
Finally, a compensation transistor TN3 is designed to reset the differential input voltage at the terminals of the differential amplifier in a balancing phase that follows the precharging phase and precedes the actual reading phase. This balancing phase makes it possible to reduce the differential voltage at the input of amplifier AD to a value that is as close as possible to zero, whatever the logic state read in a memory state at the previous reading stage. Transistor TN3 is, for example, an N channel transistor that is made conductive during a balancing stage EQ.
The stage of reading a memory cell of this type of memory therefore comprises a phase for precharging the bit line associated with the memory cell, a phase of balancing between the associated bit line and the corresponding reference line and a phase for the actual reading of the memory cell. The time taken to read a memory cell of a non-volatile memory of this type is about 30 nanoseconds.
An aim of the invention is to reduce the time for reading the cells of a non-volatile memory. Thus, the invention proposes a memory structure that can be used to eliminate the stages for the precharging and balancing of the bit lines of the memory array.
To improve the time of reading of the cells, the present invention proposes the storage of the information elements by the use of two memory cells, one programmed and the other erased.
To implement this solution, it is necessary to modify the structure of the memory array as well as that of the associated read circuits.